1. Field of the Invention
The present invention generally relates to a serial data detection circuit and a received data signal processing device, and more particularly, to a serial data detection circuit and a received data signal processing device using the serial data detection circuit which are used in a high-speed serial communication system using a USB and so forth.
2. Description of the Related Art
Recently, products have been provided with a high-speed interface, and systems using high-speed serial communications have been developed. Such high-speed serial communications include a high-speed serial communication using a USB, for example. USB standards include USB 1.1; however, systems using USB 2.0 achieving a communication speed of 480 Mbps faster than USB 1.1 have been developed. Upon receiving data by these systems, an amplitude level of a signal is used in judging whether or not a transmission medium is connected, and whether or not received data exists. When the level exceeds a predetermined threshold value, a predetermined signal reproduction processing is applied to the received data. When the level does not exceed the predetermined threshold value, the predetermined signal reproduction processing is not applied to the received data.
FIG. 1 is a block diagram of a conventional example of a received data signal processing device 100 conforming to the foregoing USB 2.0 standard.
As shown in FIG. 1, the received data signal processing device 100 comprises a normal receiver 101, a digital signal processing circuit 102, and a signal lines DP and DM.
Further, the received data signal processing device 100 comprises an integration circuit 104 and a Schmitt circuit 105. The integration circuit 104 integrates an output signal (OUTb) of the signal detection receiver 103, and outputs the integrated signal. The Schmitt circuit 105 applies a waveform shaping to the output signal of the integration circuit 104, generates a receiver enable signal RE used for performing an enabling control of the normal receiver 101, and outputs the receiver enable signal RE to the normal receiver 101. The signal detection receiver 103, the integration circuit 104 and the Schmitt circuit 105 together form a serial data detection circuit 106 that detects whether or not serial data signals are supplied from the serial transmission lines DP and DM, and performs a driving control of the normal receiver 101 according to a result of the detection.
In a system using a USB and so forth, nodes of the serial transmission lines DP and DM become low-level in an idle state. In this state, the output of the normal receiver 101 becomes unstable so that problems occur in the signal processing performed by the digital signal processing circuit 102. For the purpose of avoiding such problems, the signal detection receiver 103 is provided so as to control the normal receiver 101 to operate only during a duration in which the signal detection receiver 103 detects serial data signals. Therefor, a threshold value is provided with an offset in the signal detection receiver 103.
FIG. 2 is a timing chart exemplifying the signals shown in FIG. 1. As mentioned above, the signal detection receiver 103 includes a threshold value provided with an offset. When the signal detection receiver 103 detects a reception of serial data signals from the serial transmission lines DP and DM, the signal detection receiver 103 generates a pulse signal corresponding to the serial data signals, and outputs the pulse signal as the output signal OUTb. The output signal OUTb is integrated by the integration circuit 104, and thereafter, is subjected to a waveform shaping by the Schmitt circuit 105 so as to be converted into a binary signal. The binary signal is output as the receiver enable signal RE to the normal receiver 101.
In other words, when the serial data detection circuit 106 detects a reception of serial data signals from the serial transmission lines DP and DM, the serial data detection circuit 106 raises the receiver enable signal RE to high level so as to cause the normal receiver 101 to operate. On the other hand, when the serial data detection circuit 106 does not detect a reception of serial data signals, the serial data detection circuit 106 makes the receiver enable signal RE low-level so as to cause the normal receiver 101 to stop operating.
FIG. 3 is a circuit diagram of an example of the signal detection receiver 103 shown in FIG. 1. In FIG. 3, the signal detection receiver 103 has a circuit configuration basically the same as a normal-type receiver except that input transistors 111 and 112 which are P-channel MOS transistors (hereinafter referred to as PMOS transistors) have different sizes so as to provide an offset. Besides, a constant bias voltage is applied to a gate of a PMOS transistor 113.
FIG. 4 is a circuit diagram of another example of the signal detection receiver 103 shown in FIG. 1.
In FIG. 4, the signal detection receiver 103 includes input transistors 121 and 122 which are PMOS transistors have identical sizes forming a differential pair. A constant current ia derived from a constant current source 130 is applied by PMOS transistors 131 to 133 to a node between the input transistor 121 and an N-channel MOS transistor (hereinafter referred to as NMOS transistor) so as to provide a threshold value with an offset.
However, with configurations such as shown in FIG. 3 and FIG. 4, there is a problem that characteristics of the transistors provided in the signal detection receiver 103 vary according to changes in processes, temperature and so forth, thereby varying the offset. In order to reduce the variation of the offset, it is conceivable that a gate area of each of the input transistors be increased. However, this not only causes a problem that an operating speed of the signal detection receiver 103 is decreased, but also involves a limit in reducing the variation of the offset.
It is a general object of the present invention to provide an improved and useful serial data detection circuit and a received data signal processing device in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a serial data detection circuit conforming to USB standards and so forth which can reduce variation of an offset and enable a high-speed operation by adjusting an amount of an offset current according to processes, temperature and so forth, and a received data signal processing device using the serial data detection circuit.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a serial data detection circuit detecting whether or not a pair of serial data signals having reciprocal signal levels are supplied, the circuit composed of a signal detection circuit unit including a differential amplification circuit providing an offset for one serial data signal of the serial data signals, and outputting a predetermined signal indicating a detection of the serial data signals when a voltage of the other serial data signal of the serial data signals becomes larger than a voltage of the one serial data signal provided with the offset, a differential amplification circuit unit providing an offset for one constant voltage of different predetermined constant voltages supplied thereto, and outputting signals by performing a differential amplification to the constant voltages, and an offset control circuit unit controlling the offset provided by the differential amplification circuit unit so that voltages of the signals output by the differential amplification circuit unit coincide, and correspondingly controlling the offset provided by the differential amplification circuit included in the signal detection circuit unit.
According to the present invention, the offset used in the signal detection circuit unit is determined according to a feedback signal used by the offset control circuit unit with respect to the differential amplification circuit unit. Accordingly, even when processes, temperature and so forth are changed, variation of the offset can be reduced; thus, a stable system conforming to USB standards and so forth can be provided. Additionally, the signal indicating the detection of the serial data signals can be generated at high speed upon receiving serial data.
Additionally, in the serial data detection circuit, the signal detection circuit unit includes a flip-flop retaining an output signal output by a receiver of the serial data detection circuit, and outputting the output signal as a signal indicating whether or not the serial data signals are detected.
According to the present invention, the serial data signals can be detected accurately and in a shortened time.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a received data signal processing device provided in a high-speed serial communication system using a USB and so forth, the device including the above-mentioned serial data detection circuit.
According to the present invention, the offset used in the signal detection circuit unit is determined according to a feedback signal used by the offset control circuit unit with respect to the differential amplification circuit unit. Accordingly, even when processes, temperature and so forth are changed, variation of the offset can be reduced; thus, the high-speed serial communication system can be made stable conforming to USB standards and so forth. Additionally, the signal indicating the detection of the serial data signals can be generated at high speed upon receiving serial data; accordingly, the reception of the serial data signals can be detected accurately, and an accurate signal processing can be performed to the received signals.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.